Dual metal gate process: metals and their silicides

ABSTRACT

Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Silicon ions are implanted into the metal layer in one active area to form an implanted metal layer which is silicided to form a metal silicide layer. Thereafter, the metal layer and the metal silicide layer are patterned to form a metal gate in one active area and a metal silicide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal silicide gates wherein the silicon concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate. A metal layer is deposited over a gate dielectric layer within the gate openings to form metal gates. One or both of the gates are silicon implanted and silicided. The PMOS gate has the higher work function.

RELATED PATENT APPLICATION

[0001] U.S. patent application Ser. No. 09/______,______ to the sameinventors, filed on ______. (CS-00-114)

BACKGROUND OF THE INVENTION

[0002] (1) Field of the Invention

[0003] The present invention relates to the fabrication of integratedcircuit devices, and more particularly, to a method of fabricatingdual-metal transistors having different work functions in thefabrication of integrated circuits.

[0004] (2) Description of the Prior Art

[0005] It is anticipated that a single metal gate with mid-gap workfunction values will not be suitable for CMOS applications due to buriedchannel effects. By using a single metal gate for both NMOSFET andPMOSFET, the threshold voltage becomes too high for both types oftransistors. In order to achieve a lower threshold voltage, additionalimplantation is required and this will result in buried channel effects.The short channel effect control will then be degraded. However, withdual metal gates having different work functions, additionalimplantation is not required. That is, one electrode with a lower workfunction will be used in the NMOSFET while another electrode with ahigher work function will be used for the PMOSFET. That means that thethreshold voltage for NMOSFET and PMOSFET can be tailored independently.It is desired to maintain the conventional CMOS process flow in the dualmetal gate process.

[0006] U.S. Pat. No. 6,043,157 to Gardner et al shows a process forforming dual gates where one gate is polysilicon and the other gate ismetal. U.S. Pat. No. 5,960,270 to Misra et al discloses a processwherein the same mid-gap work function metal is used for both n- andp-gates. U.S. Pat. No. 6,083,836 to Rodder teaches a dummy gate processwhere two gates are formed. For example, one gate is polysilicon and theother is aluminum. U.S. Pat. No. 6,051,487 to Gardner et al teaches adummy gate process using a polysilicon or a metal gate.

SUMMARY OF THE INVENTION

[0007] Accordingly, a primary object of the invention is to provide aprocess for forming dual metal gates for CMOS transistors in thefabrication of integrated circuits.

[0008] A further object of the invention is to provide a process forforming dual-metal gate CMOS transistors having different work functionsin the fabrication of integrated circuits.

[0009] Another object of the invention is to provide a process forforming dual-metal gate CMOS transistors where one gate comprises ametal and the other gate comprises the metal's silicide.

[0010] Yet another object of the invention is to provide a process forforming dual-metal gate CMOS transistors comprising a metal and themetal silicide.

[0011] A still further object of the invention is to provide a processfor forming dual-metal gate CMOS transistors comprising a first metalsilicide and a second metal silicide wherein the metal is the same inboth gates and the silicide concentration is different.

[0012] In accordance with the objects of the invention, a method forforming dual-metal gate CMOS transistors is achieved. First and secondactive areas of a semiconductor substrate are separated by isolationregions. One of the active areas will be PMOS and the other will beNMOS. A gate dielectric layer is formed overlying the semiconductorsubstrate in each of the active areas. A metal layer is depositedoverlying the gate dielectric layer. Silicon ions are implanted into themetal layer in the PMOS area to form an implanted metal layer and theimplanted metal layer is silicided to form a metal silicide layer.Thereafter, the metal layer and the metal silicide layer are patternedto form a metal gate in a first active area and a metal silicide gate ina second active area to complete formation of dual-metal gate CMOStransistors in the fabrication of an integrated circuit. The metalsilicide may have a higher or lower work function depending on the metalused. The PMOS gate will be formed from the gate having the higher workfunction.

[0013] Also, in accordance with the objects of the invention, a secondmethod for forming dual-metal gate CMOS transistors is achieved. Firstand second active areas of a semiconductor substrate are separated byisolation regions. One of the active areas will be PMOS and the otherwill be NMOS. A dummy gate is formed in each of the active areas. Thedummy gates are covered with a dielectric layer which is planarizedwhereby a top surface of each of the dummy gates is exposed. The exposeddummy gates are removed, leaving gate openings to the semiconductorsubstrate. A gate dielectric layer is formed overlying the semiconductorsubstrate in each of the gate openings. A metal layer is depositedwithin the gate openings to form metal gates. Silicon ions are implantedinto the metal gate only in a first active area to form an implantedmetal gate. The implanted metal gate is silicided to form a metalsilicide gate in the first active area to complete formation ofdual-metal gate CMOS transistors in the fabrication of an integratedcircuit. The metal silicide may have a higher or lower work functiondepending on the metal used. The PMOS gate will be formed from the gatehaving the higher work function.

[0014] Also, in accordance with the objects of the invention, a thirdmethod for forming dual-metal gate CMOS transistors is achieved. Firstand second active areas of a semiconductor substrate are separated byisolation regions. One of the active areas will be PMOS and the otherwill be NMOS. A gate dielectric layer is formed overlying thesemiconductor substrate in each of the active areas. A metal layer isdeposited overlying the gate dielectric layer. First silicon ions areimplanted into the metal layer in a first active area to form animplanted metal layer and the implanted metal layer is silicided to forma first metal silicide layer. Second silicon ions are implanted into themetal layer in the second active area to form an implanted metal layerand the implanted metal layer is silicided to form a second metalsilicide layer wherein the silicon concentration in the second metalsilicide layer is higher than the silicon concentration in the firstmetal silicide layer. Thereafter, the first metal silicide layer and thesecond metal silicide layer are patterned to form a first metal silicidegate in the first area and a second metal silicide gate in the secondarea to complete formation of dual-metal gate CMOS transistors in thefabrication of an integrated circuit. The PMOS gate will be formed fromthe gate having the higher work function.

[0015] Also, in accordance with the objects of the invention, a fourthmethod for forming dual-metal gate CMOS transistors is achieved. Firstand second active areas of a semiconductor substrate are separated byisolation regions. One of the active areas will be PMOS and the otherwill be NMOS. A dummy gate is formed in each of the active areas. Thedummy gates are covered with a dielectric layer which is planarizedwhereby a top surface of each of the dummy gates is exposed. The exposeddummy gates are removed, leaving gate openings to the semiconductorsubstrate. A gate dielectric layer is formed overlying the semiconductorsubstrate in each of the gate openings. A metal layer is depositedwithin the gate openings to form metal gates. First silicon ions areimplanted into the metal gate only in a first active area to form animplanted metal gate. The implanted metal gate is silicided to form afirst metal silicide gate in the first active area. Second silicon ionsare implanted into the metal gate in the second active area to form animplanted metal gate and the implanted metal gate is silicided to form asecond metal silicide gate wherein the silicon concentration in thesecond metal silicide gate is different from the silicon concentrationin the first metal silicide gate to complete formation of dual-metalgate CMOS transistors in the fabrication of an integrated circuit. ThePMOS gate will be formed from the gate having the higher work function.

[0016] Also, in accordance with the objects of the invention, adual-metal gate CMOS integrated circuit device is achieved. The devicecomprises first and second active areas of a semiconductor substrateseparated by isolation regions. One of the active areas will be PMOS andthe other will be NMOS. A metal gate in the first active area overlies agate dielectric layer, and a metal silicide gate in the second activearea overlies a gate dielectric layer wherein the metal in the metalgate is the same material as the metal in the metal silicide gate. Themetal silicide may have a higher or lower work function depending on themetal used. The PMOS gate will be formed from the gate having the higherwork function.

[0017] Also, in accordance with the objects of the invention, anotherdual-metal gate CMOS integrated circuit device is achieved. The devicecomprises first and second active areas of a semiconductor substrateseparated by isolation regions. One of the active areas will be PMOS andthe other will be NMOS. A first metal silicide gate in the first activearea overlies a gate dielectric layer, and a second metal silicide gatein the second active area overlies a gate dielectric layer wherein themetal in the two gates is the same metal and the silicon concentrationis different in each of the two gates. The PMOS gate will be formed fromthe gate having the higher work function.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In the accompanying drawings forming a material part of thisdescription, there is shown:

[0019]FIGS. 1 through 5 are cross-sectional representations of a firstpreferred embodiment of the present invention.

[0020]FIGS. 6 through 11 are cross-sectional representations of a secondpreferred embodiment of the present invention.

[0021]FIGS. 12 and 13 are cross-sectional representations of twoalternatives of a third preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The present invention uses a metal and its metal silicide to formdual-metal gates having different work functions. In one embodiment, twodifferent suicides of the metal are used as the dual-metal gates. Itwill be understood by those skilled in the art that the invention shouldnot be limited to the embodiments described herein, but can be extendedand applied to any application in which it is desired to have metalgates having differing work functions. The first embodiment of theinvention will be described with reference to FIGS. 1-5. The secondembodiment of the invention will be described with reference to FIGS.6-11. The third embodiment of the invention will be described withreference to FIGS. 12 and 13.

[0023] Referring now to FIGS. 1-5, the first preferred embodiment of thepresent invention will be described. Referring now more particularly toFIG. 1, there is shown a semiconductor substrate 10. This is preferablymonocrystalline silicon. Isolation regions, such as shallow trenchisolation (STI) 12, are formed in the substrate to separate activeregions. N-wells and P-wells, not shown, may be formed within thesubstrate, as is conventional. Punchthrough and threshold voltageadjustment implantations, not shown, are made as is conventional in theart.

[0024] A gate dielectric layer 14 is grown or deposited over substrateto a thickness of between about 15 and 150 Angstroms. For example, thedielectric layer may be a low dielectric constant material such assilicon dioxide, nitrided silicon dioxide, silicon nitride, or theircombinations. Alternatively, the dielectric layer may be a highdielectric constant gate dielectric material such as zirconium oxide,hafnium oxide, aluminum oxide, tantalum pentoxide, barium strontiumtitanates, and crystalline oxide.

[0025] Referring now to FIG. 2, a metal layer 16 is formed over the gatedielectric layer to a thickness of between about 500 and 3000 Angstroms.The metal layer 16 may be formed by sputtering, evaporation, chemicalvapor deposition (CVD), or electroplating. The deposited metal can beplatinum, titanium, nickel, cobalt, tantalum, molybdenum, tungsten,zirconium, hafnium, vanadium, palladium, or chromium.

[0026] Now, the metal layer is masked 20, as shown in FIG. 3, to exposea region where the metal will be silicided. Silicon ions are implanted24 into the metal layer 16 where it is not covered by the mask 20.Silicon ions are implanted with a dosage of between about 5 E 15 to 5 E17 ions/cm² and an energy of between about 1 to 50 KeV. It is importantthat the masking layer is thick enough to protect the underlying metallayer from implantation. The silicidation process is now to beaccomplished by annealing in an inert gas ambient. Annealing can beperformed in a furnace, rapid thermal process (RTP), or a laser system.The photomask must be removed prior to annealing in the inert gas.Silicided metal region 28 is the result of the silicidation process.

[0027] Referring now to FIG. 4, the metal and metal silicide layers, 16and 28, respectively, are patterned to form gate electrodes. A chemicalmechanical polishing (CMP) process may be applied to achieveplanarization. In one embodiment, the silicide 28 is patterned to formthe first gate electrode and, subsequently, the metal layer is patternedto form the second gate electrode. In another embodiment, both gateelectrodes are defined and etched at the same time. The etching can beachieved by alternating chemistry 1 and chemistry 2 with time and usinga high selectivity etch chemistry when the etch process is getting closeto the end point, with chemistry 1 having a higher etch rate forsilicide and chemistry 2 having a higher etch rate for the metal, orvice versa. Thus, metal gates 16 and 28, having different workfunctions, are realized.

[0028] The metal silicide gate 28 may have a higher or lower workfunction than the metal gate 16 depending on the metal used. The PMOSgate will be the gate having the higher work function and the NMOS gatewill be the gate having the lower work function.

[0029] Referring now to FIG. 5, source/drain regions 30 and sidewallspacers 32 may be formed, as is conventional. The spacers 32 maycomprise either silicon nitride or silicon oxide. Processing continuesas is conventional in the art, except that silicidation over the gatesis not required.

[0030] The second preferred embodiment of the present invention will bedescribed with reference to FIGS. 6-11. This embodiment is a damascenegate process. Referring now more particularly to FIG. 6, there is showna semiconductor substrate 10. This is preferably monocrystallinesilicon. Isolation regions, such as shallow trench isolation (STI) 12,are formed in the substrate to separate active regions. N-wells andP-wells, not shown, may be formed within the substrate, as isconventional. Punchthrough and threshold voltage adjustmentimplantations, not shown, are made as is conventional in the art.

[0031] Dummy gates are formed. A first layer of silicon oxide 42 isdeposited over the substrate to a thickness of between about 15 and 150Angstroms. A layer of silicon nitride 44 is deposited over the siliconoxide layer 42 to a thickness of between about 15 and 200 Angstroms. Alayer of polysilicon 46 is deposited over the silicon nitride layer 44to a thickness of between about 500 and 3000 Angstroms. The dummy gatestack is patterned to form a dummy gate 50 in each of the active areas,as shown in FIG. 6. Sidewall spacers 54 and source/drain regions 52 areformed as is conventional in the art. Now, an interlevel dielectriclayer 58 is deposited over the dummy gates and planarized to the top ofthe dummy gates by CMP.

[0032] As shown in FIG. 7, the dummy gates 50 are removed where they areexposed by the CMP process. The dummy gates are removed by wet etching,dry etching, or a combination of the two.

[0033] Now, the dual-metal gates of the present invention are to beformed. A gate dielectric layer 60 is deposited or thermally grown onthe exposed substrate surface within the gate openings to a thickness ofbetween about 15 and 150 Angstroms, as shown in FIG. 8. As in the firstembodiment, the dielectric layer may be a low dielectric constantmaterial such as silicon dioxide, nitrided silicon dioxide, siliconnitride, or their combinations or a high dielectric constant gatedielectric material such as zirconium oxide, hafnium oxide, aluminumoxide, tantalum pentoxide, barium strontium titanates, and crystallineoxide.

[0034] Referring now to FIG. 9, a metal layer 62 is formed over the gatedielectric layer 60. The metal layer 62 may be deposited by sputteringor CVD, for example. The deposited metal can be platinum, titanium,nickel, cobalt, tantalum, molybdenum, tungsten, zirconium, hafnium,vanadium, palladium, or chromium. A CMP process polishes away the metallayer not within the gate openings, thus completing the damasceneprocess.

[0035] Now, as shown in FIG. 10, a photomask 65 is formed to cover theintermetal dielectric layer 58 and the first gate. An opening is formedin the photomask to expose only the second gate that is to be silicided.Silicon ions are implanted 69 by a low energy implanter into the secondgate where it is not covered by the mask 65. Silicon ions are implantedwith a dosage of between about 5 E 15 to 5 E 17 ions/cm² and an energyof between about 1 to 50 KeV. It is important that the masking layer isthick enough to protect the first gate from implantation.

[0036] After stripping the photomask 65, an annealing step in an inertgas or a vacuum is performed to form a silicide from thesilicon-implanted metal 72.

[0037] As shown in FIG. 11, metal gates 62 and 72, having different workfunctions, are realized. Gate 62 comprises a metal while gate 72comprises metal silicide. The gate electrode with the higher workfunction will be the PMOSFET while the gate electrode with the lowerwork function will be the NMOSFET.

[0038] The work functions of the gate electrodes of the first twoembodiments have been measured as shown in Table 1. The resistivity ofalmost all metals and their suicides is much lower than the resistivityof polysilicon. TABLE 1 gate material work func (eV) Pt 5.32-5.5 PtSi₂^(˜)4.62 Ti 3.95-4.33 TiSi₂ ^(˜)4.38 Ni 4.5-5.3 NiSi₂ ^(˜)4.55 Co4.41-5.00 CoSi₂ ^(˜)4.52 Ta 4.12-4.25 TaSi₂ ^(˜)4.35 Mo 4.3-4.6 MoSi₂^(˜)4.42 W 4.1-5.2 WSi₂ ^(˜)4.43 Zr 3.9-4.05 ZrSi₂ ^(˜)4.33 Hf N/A HfSi₂N/A V 4.12-4.3 VSi₂ ^(˜)4.37 Pd 4.8-5.22 PdSi ^(˜)4.6 Cr 4.5-4.6 CrSi₂^(˜)4.41

[0039] The dual-metal gate can also be realized by adjusting the workfunction of the silicides since the work function of the metal silicidesis closely related to the stoichiometry. That is, one gate electrodewill be in the form of MSi_(X) while the other gate electrode will be inthe form of MSi_(Y), where M is a metal which can be platinum, titanium,nickel, cobalt, tantalum, molybdenum, tungsten, zirconium, hafnium,vanadium, palladium, or chromium, and X is not equal to Y. The value ofX and Y can be well adjusted by the implantation dose. The methodsdescribed for the first and second embodiments can also be used in thisthird embodiment dual-gate process.

[0040] As shown in FIG. 12, the conventional gate formation processdescribed in the first embodiment can be used to form the two gatesMSi_(X) and MSi_(Y). The metal layer can be implanted with two differentdosages of silicon ions to form these two metal silicide gates havingdifferent work functions. For example, a first silicon ion dosage ofbetween about 1 E 15 and 1 E 16 ions/cm² will form a gate having a lowerwork function and a second silicon ion dosage of between about 1 E 16and 1 E 17 ions/cm² will form a gate having a higher work function.

[0041] Alternatively, instead of depositing an elemental metal layer forgate electrode 1, a silicide with a certain M/Si ratio can be depositedby CVD or sputtering. This will form the first gate electrode MSi_(X).The stoichiometry of the second electrode MSi_(Y) can be adjusted by thesilicon ion implantation as described with for the first embodiment. Forexample, the silicon concentration of the first gate electrode having alower work function is between about 1 E 21 and 1 E 22 ions/cm³ and thesilicon concentration of the second gate electrode having a higher workfunction is between about 1 E 22 and 1 E 23 ions/cm³.

[0042] As shown in FIG. 13, the damascene gate process described in thesecond embodiment can be used to form the two gates MSi_(X) and MSi_(Y).The gates will each be implanted with different dosages of silicon ionsto form these two metal silicide gates having different work functions.Again, as an alternative, instead of depositing an elemental metal layerfor gate electrode 1, a silicide with a certain M/Si ratio can bedeposited by CVD or sputtering. This will form the first gate-electrodeMSi_(X). The stoichiometry of the second electrode MSi_(Y) can beadjusted by the silicon ion implantation as described with for thesecond embodiment.

[0043] The process of the present invention provides three simple,manufacturable dual-metal gate processes. The conventional CMOS processflow is maintained. The work function of the gates is simply tuned bythe silicidation process. The dual-metal gates comprise a metal and ametal silicide, or two metal silicides having different work functions.The metal silicide having the higher work function will be used for thePMOS gate and the metal silicide having the lower work function will beused for the NMOS gate.

[0044] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetails may be made without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A method of forming dual-metal gate CMOS transistors in the fabrication of integrated circuits comprising: providing a first and a second active area of a semiconductor substrate separated by isolation regions wherein one of said active areas will be a PMOS area and the other of said active areas will be an NMOS area; forming a gate dielectric layer overlying said semiconductor substrate in each of said active areas; depositing a metal layer overlying said gate dielectric layer; implanting silicon ions into said metal layer in said first active area to form an implanted metal layer and siliciding said implanted metal layer to form a metal silicide layer; and thereafter patterning said metal layer and said metal silicide layer to form a metal gate in said second active area and a metal silicide gate in said first active area wherein said PMOS area comprises one of said first and second active areas having a gate having a higher work function than said gate in the other of said active areas to complete formation said of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.
 2. The method according to claim 1 wherein said gate dielectric layer is selected from the group containing silicon dioxide, nitrided silicon dioxide, silicon nitride, and a combination thereof.
 3. The method according to claim 1 wherein said gate dielectric layer is selected from the group containing zirconium oxide, hafnium oxide, aluminum oxide, tantalum pentoxide, barium strontium titanates, and crystalline oxides.
 4. The method according to claim 1 wherein said metal layer is selected from the group containing platinum, titanium, nickel, cobalt, tantalum, molybdenum, tungsten, zirconium, hafnium, vanadium, palladium, and chromium.
 5. The method according to claim 1 wherein said silicon ions are implanted at a dosage of between about 5 E 15 and 5 E 17 ions/cm² and an energy of between about 1 and 50 KeV.
 6. The method according to claim 1 wherein said step of siliciding said implanted metal layer comprises annealing in an inert gas and wherein said annealing is performed in one of the group of: a furnace process, a rapid thermal process, and a laser process.
 7. A method of forming dual-metal gate CMOS transistors in the fabrication of integrated circuits comprising: providing a first and a second active area of a semiconductor substrate separated by isolation regions wherein one of said active areas will be a PMOS area and the other of said active areas will be an NMOS area; forming a dummy gate in each of said active areas; covering said dummy gates with a dielectric layer; planarizing said dielectric layer whereby a top surface of each of said dummy gates is exposed; removing said exposed dummy gates leaving gate openings to said semiconductor substrate; forming a gate dielectric layer overlying said semiconductor substrate in each of said gate openings; depositing a metal layer within said gate openings to form metal gates; and implanting silicon ions into said metal gate only in said first active area to form an implanted metal gate and siliciding said implanted metal gate to form a metal silicide gate in said first active area wherein said PMOS area comprises one of said first and second active areas having a gate having a higher work function than said gate in the other of said active areas to complete formation said of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.
 8. The method according to claim 7 wherein said dummy gates comprise a first layer of silicon dioxide, a second layer of silicon nitride, and a third layer of polysilicon.
 9. The method according to claim 7 wherein said step of removing said dummy gates is selected from the group containing: wet etching, dry etching, and a combination of wet and dry etching.
 10. The method according to claim 7 wherein said gate dielectric layer is selected from the group containing silicon dioxide, nitrided silicon dioxide, silicon nitride, and a combination thereof.
 11. The method according to claim 7 wherein said gate dielectric layer is selected from the group containing zirconium oxide, hafnium oxide, aluminum oxide, tantalum pentoxide, barium strontium titanates, and crystalline oxides.
 12. The method according to claim 7 wherein said metal layer is selected from the group containing platinum, titanium, nickel, cobalt, tantalum, molybdenum, tungsten, zirconium, hafnium, vanadium, palladium, and chromium.
 13. The method according to claim 7 wherein said silicon ions are implanted at a dosage of between about 5 E 15 and 5 E 17 ions/cm² and an energy of between about 1 and 50 KeV.
 14. The method according to claim 7 wherein said step of siliciding said implanted metal layer comprises annealing in an inert gas or vacuum wherein said annealing is performed in one of the group of: a furnace process, a rapid thermal process, and a laser process.
 15. A method of forming dual-metal gate CMOS transistors in the fabrication of integrated circuits comprising: providing a first and a second active area of a semiconductor substrate separated by isolation regions wherein one of said active areas will be a PMOS area and the other of said active areas will be an NMOS area; forming a gate dielectric layer overlying said semiconductor substrate in each of said active areas; depositing a metal layer overlying said gate dielectric layer; implanting first silicon ions into said metal layer in said first active area to form an implanted metal layer and siliciding said implanted metal layer to form a first metal silicide layer; implanting second silicon ions into said metal layer in said second active area to form an implanted metal layer and siliciding said implanted metal layer to form a second metal silicide layer wherein said first metal silicide layer has a different silicon concentration from said second metal silicide layer; and thereafter patterning said first and second metal silicide layers to form a first metal silicide gate in said first active area and a second metal silicide gate in said second active area wherein said PMOS area comprises one of said first and second active areas having a gate having a higher work function than said gate in the other of said active areas to complete formation said of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.
 16. The method according to claim 15 wherein said gate dielectric layer is selected from the group containing silicon dioxide, nitrided silicon dioxide, silicon nitride, and a combination thereof.
 17. The method according to claim 15 wherein said gate dielectric layer is selected from the group containing zirconium oxide, hafnium oxide, aluminum oxide, tantalum pentoxide, barium strontium titanates, and crystalline oxides.
 18. The method according to claim 15 wherein said metal layer is selected from the group containing platinum, titanium, nickel, cobalt, tantalum, molybdenum, tungsten, zirconium, hafnium, vanadium, palladium, and chromium.
 19. The method according to claim 15 wherein said first silicon ions are implanted at a dosage of between about 5 E 15 and 5 E 16 ions/cm² and an energy of between about 1 and 50 KeV.
 20. The method according to claim 15 wherein said second silicon ions are implanted at a dosage of between about 5 E 16 and 5 E 17 ions/cm² and an energy of between about 1 and 50 KeV.
 21. The method according to claim 15 wherein said steps of siliciding said implanted metal layer comprises annealing in an inert gas wherein said annealing is performed in one of the group of: a furnace process, a rapid thermal process, and a laser process.
 22. A method of forming dual-metal gate CMOS transistors in the fabrication of integrated circuits comprising: providing a first and a second active area of a semiconductor substrate separated by isolation regions wherein one of said active areas will be a PMOS area and the other of said active areas will be an NMOS area; forming a dummy gate in each of said active areas; covering said dummy gates with a dielectric layer; planarizing said dielectric layer whereby a top surface of each of said dummy gates is exposed; removing said exposed dummy gates leaving gate openings to said semiconductor substrate; forming a gate dielectric layer overlying said semiconductor substrate in each of said gate openings; depositing a metal layer within said gate openings to form metal gates; implanting first silicon ions into said metal gate only in said first active area to form an implanted metal gate and siliciding said implanted metal gate to form a first metal silicide gate in said first active area; and implanting second silicon ions into said metal gate only in said second active area to form an implanted metal gate and siliciding said implanted metal gate to form a second metal silicide gate in said second active area wherein said PMOS area comprises one of said first and second active areas having a gate having a higher work function than said gate in the other of said active areas to complete formation said of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.
 23. The method according to claim 22 wherein said dummy gates comprise a first layer of silicon dioxide, a second layer of silicon nitride, and a third layer of polysilicon.
 24. The method according to claim 22 wherein said step of removing said dummy gates is selected from the group containing: wet etching, dry etching, and a combination of wet and dry etching.
 25. The method according to claim 22 wherein said gate dielectric layer is selected from the group containing silicon dioxide, nitrided silicon dioxide, silicon nitride, and a combination thereof.
 26. The method according to claim 22 wherein said gate dielectric layer is selected from the group containing zirconium oxide, hafnium oxide, aluminum oxide, tantalum pentoxide, barium strontium titanates, and crystalline oxides.
 27. The method according to claim 22 wherein said metal layer is selected from the group containing platinum, titanium, nickel, cobalt, tantalum, molybdenum, tungsten, zirconium, hafnium, vanadium, palladium, and chromium.
 28. The method according to claim 22 wherein said first silicon ions are implanted at a dosage of between about 5 E 15 and 5 E 16 ions/cm² and an energy of between about 1 and 50 KeV.
 29. The method according to claim 22 wherein said second silicon ions are implanted at a dosage of between about 5 E 16 and 5 E 17 ions/cm² and an energy of between about 1 and 50 KeV.
 30. The method according to claim 22 wherein said steps of siliciding said implanted metal layer comprises annealing in an inert gas or vacuum wherein said annealing is performed in one of the group of: a furnace process, a rapid thermal process, and a laser process.
 31. A method of forming dual-metal gate CMOS transistors in the fabrication of integrated circuits comprising: providing a first and a second active area of a semiconductor substrate separated by isolation regions wherein one of said active areas will be a PMOS area and the other of said active areas will be an NMOS area; forming a gate dielectric layer overlying said semiconductor substrate in each of said active areas; depositing a first metal silicide layer overlying said gate dielectric layer; implanting silicon ions into said first metal silicide layer in said first active area and siliciding implanted said first metal silicide layer to form a second metal silicide layer having a different silicon concentration than said first metal silicide layer; and thereafter patterning said first and second metal silicide layers to form a first metal silicide gate in said first active area and a second metal silicide gate in said second active area wherein said PMOS area comprises one of said first and second active areas having a gate having a higher work function than said gate in the other of said active areas to complete formation said of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.
 32. The method according to claim 31 wherein said gate dielectric layer is selected from the group containing silicon dioxide, nitrided silicon dioxide, silicon nitride, and a combination thereof.
 33. The method according to claim 31 wherein said gate dielectric layer is selected from the group containing zirconium oxide, hafnium oxide, aluminum oxide, tantalum pentoxide, barium strontium titanates, and crystalline oxides.
 34. The method according to claim 31 wherein said first metal silicide layer is selected from the group containing platinum silicide, titanium silicide, nickel silicide, cobalt silicide, tantalum silicide, molybdenum silicide, tungsten silicide, zirconium silicide, hafnium silicide, vanadium silicide, palladium silicide, and chromium silicide.
 35. The method according to claim 31 wherein said steps of siliciding said implanted metal layer comprises annealing in an inert gas wherein said annealing is performed in one of the group of: a furnace process, a rapid thermal process, and a laser process.
 36. A method of forming dual-metal gate CMOS transistors in the fabrication of integrated circuits comprising: providing a first and a second active area of a semiconductor substrate separated by isolation regions wherein one of said active areas will be a PMOS area and the other of said active areas will be an NMOS area; forming a dummy gate in each of said active areas; covering said dummy gates with a dielectric layer; planarizing said dielectric layer whereby a top surface of each of said dummy gates is exposed; removing said exposed dummy gates leaving gate openings to said semiconductor substrate; forming a gate dielectric layer overlying said semiconductor substrate in each of said gate openings; depositing a first metal silicide layer within said gate openings to form first metal silicide gates; and implanting silicon ions into said metal silicide gate only in said first active area to form an implanted metal silicide gate and siliciding said implanted metal silicide gate to form a second metal silicide gate in said first active area wherein said PMOS area comprises one of said first and second active areas having a gate having a higher work function than said gate in the other of said active areas to complete formation said of dual-metal gate CMOS transistors in the fabrication of an integrated circuit.
 37. The method according to claim 36 wherein said dummy gates comprise a first layer of silicon dioxide, a second layer of silicon nitride, and a third layer of polysilicon.
 38. The method according to claim 36 wherein said step of removing said dummy gates is selected from the group containing: wet etching, dry etching, and a combination of wet and dry etching.
 39. The method according to claim 36 wherein said gate dielectric layer is selected from the group containing silicon dioxide, nitrided silicon dioxide, silicon nitride, and a combination thereof.
 40. The method according to claim 36 wherein said gate dielectric layer is selected from the group containing zirconium oxide, hafnium oxide, aluminum oxide, tantalum pentoxide, barium strontium titanates, and crystalline oxides.
 41. The method according to claim 36 wherein said metal silicide layer is selected from the group containing platinum silicide, titanium silicide, nickel silicide, cobalt silicide, tantalum silicide, molybdenum silicide, tungsten silicide, zirconium silicide, hafnium silicide, vanadium silicide, palladium silicide, and chromium silicide.
 42. The method according to claim 36 wherein said step of siliciding said implanted metal silicide layer comprises annealing in an inert gas or vacuum wherein said annealing is performed in one of the group of: a furnace process, a rapid thermal process, and a laser process.
 43. A dual-metal gate CMOS integrated circuit device comprising: an NMOS active area and a PMOS active area of a semiconductor substrate separated by isolation regions; a metal gate in said NMOS area over a gate dielectric layer; and a metal silicide gate in said PMOS area over a gate dielectric layer wherein said metal in said metal gate is the same material as said metal in said metal silicide gate and wherein said metal silicide gate in said PMOS area has a higher work function than said metal gate in said NMOS area.
 44. The device according to claim 43 wherein said gate dielectric layer is selected from the group containing silicon dioxide, nitrided silicon dioxide, silicon nitride, and a combination thereof.
 45. The device according to claim 43 wherein said gate dielectric layer is selected from the group containing zirconium oxide, hafnium oxide, aluminum oxide, tantalum pentoxide, barium strontium titanates, and crystalline oxides.
 46. The device according to claim 43 wherein said metal layer is selected from the group containing platinum, titanium, nickel, cobalt, tantalum, molybdenum, tungsten, zirconium, hafnium, vanadium, palladium, and chromium.
 47. A dual-metal gate CMOS integrated circuit device comprising: an NMOS active area and a PMOS active area of a semiconductor substrate separated by isolation regions; a metal gate in said PMOS area over a gate dielectric layer; and a metal silicide gate in said NMOS area over a gate dielectric layer wherein said metal in said metal gate is the same material as said metal in said metal silicide gate and wherein said metal gate in said PMOS area has a higher work function than said metal silicide gate in said NMOS area.
 48. The device according to claim 47 wherein said gate dielectric layer is selected from the group containing silicon dioxide, nitrided silicon dioxide, silicon nitride, and a combination thereof.
 49. The device according to claim 47 wherein said gate dielectric layer is selected from the group containing zirconium oxide, hafnium oxide, aluminum oxide, tantalum pentoxide, barium strontium titanates, and crystalline oxides.
 50. The device according to claim 47 wherein said metal layer is selected from the group containing platinum, titanium, nickel, cobalt, tantalum, molybdenum, tungsten, zirconium, hafnium, vanadium, palladium, and chromium.
 51. A dual-metal gate CMOS integrated circuit device comprising: an NMOS active area and a PMOS active area of a semiconductor substrate separated by isolation regions; a first metal silicide gate in said NMOS area over a gate dielectric layer; and a second metal silicide gate in said PMOS area over a gate dielectric layer wherein said metal in said first metal silicide gate is the same material as said metal in said second metal silicide gate and wherein the concentration of silicon in said first metal silicide gate is different from said the concentration of silicon in said second metal silicide gate and wherein said second metal silicide gate has a higher work function than said first metal silicide gate.
 52. The device according to claim 51 wherein said gate dielectric layer is selected from the group containing silicon dioxide, nitrided silicon dioxide, silicon nitride, and a combination thereof.
 53. The device according to claim 51 wherein said gate dielectric layer is selected from the group containing zirconium oxide, hafnium oxide, aluminum oxide, tantalum pentoxide, barium strontium titanates, and crystalline oxides.
 54. The device according to claim 51 wherein said metal silicide is selected from the group containing platinum silicide, titanium silicide, nickel silicide, cobalt silicide, tantalum silicide, molybdenum silicide, tungsten silicide, zirconium silicide, hafnium silicide, vanadium silicide, palladium silicide, and chromium silicide. 